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Posted 20 July, 2026

IC Design Layout Engineer (Contract)

Morson Edge
Portsmouth, ENG, GB Full Time

Job Description

IC Design Layout Engineer (Contract)

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Location: REMOTE
Duration: 6 Months (Inside IR35)

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Rate: £53.70 per hour Umbrella

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We seek an engineer with recent high-integrity or safety-critical industry experience (defence, aerospace, or similar), or eligible for UK security clearance.

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Overview

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An exciting opportunity is available for an experienced IC Design Layout Engineer to join a multidisciplinary electronics team working on advanced mixed-signal semiconductor technologies. The successful candidate will contribute to the physical implementation and verification of complex analogue and mixed-signal integrated circuits, collaborating closely with circuit designers to deliver high-quality layouts to demanding project schedules.

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Key Responsibilities

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  • Translate transistor, cell and block-level schematics into robust physical layouts.
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  • Produce bespoke analogue, digital and mixed-signal IC layouts in accordance with design specifications.
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  • Apply layout best practices to optimise performance, manufacturability and reliability.
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  • Perform physical verification including:
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  • Design Rule Checks (DRC)
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  • Layout Versus Schematic (LVS)
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  • Support top-level integration and verification activities where required.
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  • Work effectively within a collaborative engineering environment to meet project milestones.
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Essential Skills & Experience

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  • Several years of experience in analogue and mixed-signal IC layout design.
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  • Strong understanding of CMOS technologies and IC design methodologies.
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  • Proficiency with Cadence design tools.
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  • Experience producing layouts from schematic designs.
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  • Hands-on experience with simulation and verification workflows.
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  • Comfortable working in Linux environments.
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  • Strong attention to detail and ability to work independently.
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Desirable Experience

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  • CMOS readout IC or imaging sensor design experience.
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  • Image sensor or pixel design knowledge.
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  • Top-level verification experience.
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  • Exposure to a range of semiconductor technology nodes.
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