IC Design Layout Engineer (Contract)
Job Description
IC Design Layout Engineer (Contract)
\nLocation: REMOTE
Duration: 6 Months (Inside IR35)
Rate: £53.70 per hour Umbrella
\nWe seek an engineer with recent high-integrity or safety-critical industry experience (defence, aerospace, or similar), or eligible for UK security clearance.
\nOverview
\nAn exciting opportunity is available for an experienced IC Design Layout Engineer to join a multidisciplinary electronics team working on advanced mixed-signal semiconductor technologies. The successful candidate will contribute to the physical implementation and verification of complex analogue and mixed-signal integrated circuits, collaborating closely with circuit designers to deliver high-quality layouts to demanding project schedules.
\nKey Responsibilities
\n- \n
- Translate transistor, cell and block-level schematics into robust physical layouts. \n
- Produce bespoke analogue, digital and mixed-signal IC layouts in accordance with design specifications. \n
- Apply layout best practices to optimise performance, manufacturability and reliability. \n
- Perform physical verification including: \n
- Design Rule Checks (DRC) \n
- Layout Versus Schematic (LVS) \n
- Support top-level integration and verification activities where required. \n
- Work effectively within a collaborative engineering environment to meet project milestones. \n
Essential Skills & Experience
\n- \n
- Several years of experience in analogue and mixed-signal IC layout design. \n
- Strong understanding of CMOS technologies and IC design methodologies. \n
- Proficiency with Cadence design tools. \n
- Experience producing layouts from schematic designs. \n
- Hands-on experience with simulation and verification workflows. \n
- Comfortable working in Linux environments. \n
- Strong attention to detail and ability to work independently. \n
Desirable Experience
\n- \n
- CMOS readout IC or imaging sensor design experience. \n
- Image sensor or pixel design knowledge. \n
- Top-level verification experience. \n
- Exposure to a range of semiconductor technology nodes. \n
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