Posted 20 July, 2026
Senior Digital Hardware Design Engineer
ZENOVO LTD
Leicester, ENG, GB
Full Time
Job Description
Job Title: Senior Digital Hardware Design EngineerLocation: Leicestershire (On-site)Salary: Up to £75k (DOE) We are seeking an experienced Senior Digital Hardware Design Engineer to join an innovative engineering team developing advanced, high-performance electronic products. This is an exciting opportunity to take ownership of complex digital hardware designs from concept through to production while working closely with multidisciplinary engineering teams.About the Role\n
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- Design and implement digital hardware including high-speed interfaces, signal processing and switching/routing architectures. \n
- Develop, simulate and verify RTL designs, ensuring timing closure, robustness, and design correctness. \n
- Define and review hardware architectures, contributing to system-level design decisions and technical trade-off analysis. \n
- Produce and review technical documentation, including specifications, schematics, and hardware test plans. \n
- Perform functional simulation, synthesis and static timing analysis targeting FPGA and/or ASIC technologies. \n
- Collaborate with firmware, software, and systems engineers to ensure successful hardware/software integration. \n
- Support hardware verification, validation, laboratory bring-up and board-level debugging. \n
- Participate in design reviews, code reviews and continuous improvement of engineering processes. \n
- Work closely with manufacturing teams to optimise designs for volume manufacture and test. \n
- Liaise with component manufacturers and suppliers to support long-term product availability. \n
- Design for reliable operation in demanding or harsh environments. \n
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- Degree (or equivalent) in Electronic Engineering, Electrical Engineering, Computer Engineering, or a related discipline. \n
- 5+ years' experience in high-speed digital hardware design. \n
- Strong understanding of digital hardware design principles, including clocking strategies, Clock Domain Crossing (CDC), reset architectures, and timing constraints. \n
- Experience with FPGA development tools. \n
- Familiarity with simulation tools including ModelSim, Questa, or similar. \n
- Experience creating and executing hardware test plans. \n
- Board-level debugging using laboratory equipment such as oscilloscopes, logic analysers and protocol analysers. \n
- Strong understanding of high-speed PCB design and signal integrity. \n
- Experience using Altium Designer. \n
- Knowledge of designing electronics for harsh operating environments. \n
