Job Description
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Title: ASICS Engineering
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Duration: Sep 7, 2026 - Mar 5, 2027
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Hours Per Week: 37.00
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Location: Farnborough
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TECHNICAL SKILLS:
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Must Have:
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\n - 5+ year of RFIC work experience
\n - AMS simulations
\n - Experience of verification simulations of complete transceiver chains RF -> Analogue
\n - Verilog-A
\n - Verilog-AMS
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Nice To Have:
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\n - Digital verification skills
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The senior engineer will take on the verification of full Rx and Tx chains of an on-going design.
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They will help setup and debug simulation testbenches, report compliance to spec and validate device register controls for test.
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The tasks will include:
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Review of block specifications.
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Simulation and reporting compliance to specifications.
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Root cause any specification failures.
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Liaising with the chip lead to integrate the designs.
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Presentation of design for block-level reviews.
